/******************************************************************************
*
* MODULE:    lcd.v
* DEVICE:     
* PROJECT:   Tarea 2 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 19:35:08
*
* ABSTRACT:  lcd Ejercicio 3
*            
*****************************************************************************/
module lcd(clk_50M,arst,rxd,txd,LCD,SF_D,rxd_o,par_error);
  
  input  clk_50M,arst;
  input  rxd;
  
  output  reg txd = 0;
  
  reg     [7:0]txd_alm;
  wire    [7:0]txd_;
  output  reg [7:0]rxd_o;
  output  reg [7:0]par_error=0;
  reg     pari;
  reg    [9:0]rxd_reg;
  reg    [4:0]cont=0;
  reg    bit=0;
 
  reg    [20:0]sin = 0;
  reg    c=0;
  reg    [3:0]sabe=0;
  reg    q1;
  reg    q2;
  
  reg    trans;
  reg    [1:0]datos=0;  
  wire   [31:0]d_in_u;
  
  output reg     [3:0]SF_D; 
  output reg     [2:0]LCD; 
    
  reg        [19:0]count=0; 
  reg        [5:0]Bit = 0;
  parameter  [1:0]let = 2'b10; 
  parameter   s0 = 6'b00_0000,
              s1 = 6'b00_0001,
              s2 = 6'b00_0010,
              s3 = 6'b00_0011,
              s4 = 6'b00_0100,
              s5 = 6'b00_0101,
              s6 = 6'b00_0110,
              s7 = 6'b00_0111,
              s8 = 6'b00_1000,
              s9 = 6'b00_1001,
              s10= 6'b00_1010,
              s11= 6'b00_1011,
              s12= 6'b00_1100,
              s13= 6'b00_1101;
              
  
  always @ (posedge clk_50M) begin
  count <= count + 1;
  if (count == 'b1011_0111_0001_1011_0000)
    begin
      Bit <= Bit + 1;
      count <= 0;
    end
    
  case (Bit) 
       s0: {LCD[1:0],SF_D[3:0]} <= 6'b00_0011;        // power-on initialization {LCD[1:0],SF_D[3:0]}
       s1: {LCD[1:0],SF_D[3:0]} <= 6'b00_0011; 
       s2: {LCD[1:0],SF_D[3:0]} <= 6'b00_0011; 
       s3: {LCD[1:0],SF_D[3:0]} <= 6'b00_0010; 
       s4: {LCD[1:0],SF_D[3:0]} <= 6'b00_0010;        // function set 
       s5: {LCD[1:0],SF_D[3:0]} <= 6'b00_1000; 
       s6: {LCD[1:0],SF_D[3:0]} <= 6'b00_0000;        // entry mode set 
       s7: {LCD[1:0],SF_D[3:0]} <= 6'b00_0110; 
       s8: {LCD[1:0],SF_D[3:0]} <= 6'b00_0000;        // display on/off control 
       s9: {LCD[1:0],SF_D[3:0]} <= 6'b00_1101; 
      s10: {LCD[1:0],SF_D[3:0]} <= 6'b00_0000;        // display clear 
      s11: {LCD[1:0],SF_D[3:0]} <= 6'b00_0001; 
      s12: {LCD[1:0],SF_D[3:0]} <= {let,rxd_o[7:4]};        // asignacion bits
      s13: {LCD[1:0],SF_D[3:0]} <= {let,rxd_o[3:0]}; 
      default: {LCD[1:0],SF_D[3:0]} <= 6'b01_0000; 
    endcase 
      LCD[2] <= ^count[19:18];  // ENABLE 
  end 
    endmodule
      

      
      
  
  
  
  
